With development of integrated circuit (IC) manufacturing technology, critical dimension of metal-oxide-semiconductor (MOS) transistor becomes smaller and smaller. In order to reduce parasitic capacitance of a gate in a MOS transistor and improve device speed, gate stack structures having a high-K gate dielectric layer and a metal gate are introduced into the MOS transistor. In order to prevent metal material of the metal gate from affecting other structures in the transistor, the gate stack structures having a high-K gate dielectric layer and a metal gate are usually fabricated using a gate last process.
A conventional method for forming a metal gate using a gate last process may include: providing a semiconductor substrate having a dummy gate structure and an interlayer dielectric layer to cover the dummy gate structure; subjecting the interlayer dielectric layer to a chemical mechanical polishing (CMP) process using the dummy gate structure as a polish stop layer; removing the dummy gate structure to form a trench; forming a high-K gate dielectric material layer on the inner wall of the trench and on the surface of the interlayer dielectric layer, and forming a metal material layer on the surface of the high-K gate dielectric material layer and to fill the trench; and polishing the metal material layer and the high-K gate dielectric material layer using a CMP process until the interlayer dielectric layer is exposed, to form a metal gate in the trench.
Because the metal gate is fabricated after an implantation in source regions and drain regions is completed, the number of subsequent processes can be reduced. And the problem that metal materials are not suitable for high temperature treatment can be resolved.
In current circuit structures such as static random access memory and inverter, etc., usually the gate of an NMOS transistor and the gate of a PMOS transistor are electrically connected together. In order to increase the degree of process integration, a photo mask is usually designed such that an NMOS transistor and a PMOS transistor share a common gate structure. Thus, chip area can be effectively reduced and process complexity can be reduced.
For example, FIG. 1 depicts a top view of a common gate structure of an NMOS transistor and a PMOS transistor formed by conventional polysilicon gate technology. FIG. 2 depicts a cross-sectional view of the common gate structure along the direction of line AA′ in FIG. 1.
The common gate structure can include: a semiconductor substrate 10 having an NMOS transistor region 01 and a PMOS transistor region 02; a common gate 11 across the NMOS transistor region 01 and the PMOS transistor region 02 having a portion of the common gate 11 located in the NMOS transistor region 01 and having another portion of the common gate 11 located in the PMOS transistor region 02; an N-type source/drain region 12 formed at both sides of the portion of common gate 11 in the NMOS transistor region 01; and a P-type source/drain region 13 formed at both sides of the other portion of common gate 11 in the PMOS transistor region 02.
With the increasing degree of chip integration, critical dimension of MOS transistor becomes smaller and smaller. Common gate of NMOS transistor and PMOS transistor also needs to use metal gate in order to reduce parasitic capacitance of the gate in the MOS transistor and increase the device speed. However, electrical resistance of the common gate formed using conventional gate last technology is undesirably high.